2026-2027 Academic Catalog 
    
    Jun 01, 2026  
2026-2027 Academic Catalog
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ECET 10900 - Digital Fundamentals


Credit Hours: 3.00. This course introduces basic gate and flip-flop logic devices and their application in combinational and sequential digital circuits. Topics include decoders, displays, encoders, multiplexers, demultiplexers, registers, and counters. Logic circuit analysis, implementation of circuits using standard IC chips or programmable logic devices, circuit testing, and troubleshooting are emphasized. Typically offered Fall.
General Education: Technology
Course Learning Outcomes
1. Calculate the third parameter using Ohm’s Law when given any two of the three parameters, voltage, current and resistance. (ABET SO1,4) 2. Calculate the time period, frequency, and duty cycle when given a periodic digital waveform. (ABET SO1,4) 3. Explain the operation, match logic symbol to appropriate gate, develop Boolean expression, and create a truth table for each gate when given logic symbols of basic logic gates such as the AND, OR, NOT, NAND, NOR, EXCLUSIVE OR and NOR. (ABET SO1,4) 4. Predict the output condition for a given set of input conditions and verify using simulation software when given a single logic gate or combination of logic gates. (ABET SO1,4) 5. Predict the proper output, compare with the given output, and determine probable fault, if any, when given a logic network with input and output conditions. (ABET SO1,4) 6. Predict outputs for given inputs (logic levels or waveforms) then verify your predictions when given an MSI network representing applications of encoders or decoders. (ABET SO1,4) 7. Predict outputs for given inputs (logic levels or waveforms) when given a MSI network representing applications of multiplexers, demultiplexers, or comparators. (ABET SO1,4) 8. Predict outputs for given inputs (logic levels or waveforms) when given a MSI network using one or more adder IC and supporting logic gates. (ABET SO1,4) 9. Compare and contrast their characteristics including fan-in, fan-out, packing density and signal levels when given specification sheets of several logic families such as TTL and CMOS. (ABET SO1,3,4)


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